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Features
* Compatible with MCS(R)-51 Products * 4K Bytes of In-System Programmable (ISP) Flash Memory * * * * * * * * * * * * * * *
- Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode)
Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a fivevector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
8-bit Microcontroller with 4K Bytes In-System Programmable Flash AT89S51
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Pin Configurations
PDIP
P1.0 P1.1 P1.2 P1.3 P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
PLCC
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
TQFP
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND PWRGND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 (A13) P2.5 (A14) P2.6 (A15) P2.7
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(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
44 43 42 41 40 39 38 37 36 35 34
(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
18 19 20 21 22 23 24 25 26 27 28
(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30 29
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
PDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P1.7 (SCK) P1.6 (MISO) P1.5 (MOSI) P1.4 P1.3 P1.2 P1.1 P1.0 VDD PWRVDD P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN
AT89S51
Block Diagram
P0.0 - P0.7 P2.0 - P2.7
VCC PORT 0 DRIVERS GND PORT 2 DRIVERS
RAM ADDR. REGISTER
RAM
PORT 0 LATCH
PORT 2 LATCH
FLASH
B REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
BUFFER TMP2 TMP1
ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS
PC INCREMENTER
PSW
PROGRAM COUNTER
PSEN ALE/PROG EA / VPP RST WATCH DOG PORT 3 LATCH TIMING AND CONTROL INSTRUCTION REGISTER DUAL DPTR
PORT 1 LATCH
ISP PORT
PROGRAM LOGIC
OSC PORT 3 DRIVERS PORT 1 DRIVERS
P3.0 - P3.7
P1.0 - P1.7
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Pin Description
VCC GND VDD PWRVDD PWRGND
Supply voltage (all packages except 42-PDIP). Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory). Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory. Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage. Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground. Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 0
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin P1.5 P1.6 P1.7 Alternate Functions MOSI (used for In-System Programming) MISO (used for In-System Programming) SCK (used for In-System Programming)
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
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Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
ALE/PROG
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (V PP ) during Flash programming.
XTAL1 XTAL2
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier 5
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Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
Table 1. AT89S51 SFR Map and Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DP0L 00000000 TL1 00000000 DP0H 00000000 TH0 00000000 DP1L 00000000 TH1 00000000 DP1H 00000000 AUXR XXX00XX0 PCON 0XXX0000 SBUF XXXXXXXX AUXR1 XXXXXXX0 WDTRST XXXXXXXX PSW 00000000 ACC 00000000 B 00000000 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H
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User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register. Table 2. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable - Bit 7 - 6 - 5 WDIDLE 4 DISRTO 3 - 2 - 1 DISALE 0
- DISALE
Reserved for future expansion Disable/Enable ALE DISALE Operating Mode 0 1 ALE is emitted at a constant rate of 1/6 the oscillator frequency ALE is active only during a MOVX or MOVC instruction
DISRTO
Disable/Enable Reset-out DISRTO 0 1 Reset pin is driven High after WDT times out Reset pin is input only
WDIDLE WDIDLE 0 1
Disable/Enable WDT in IDLE mode
WDT continues to count in IDLE mode WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
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Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1" during power up. It can be set and rest under software control and is not affected by reset. Table 3. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable - Bit 7 - 6 - 5 - 4 - 3 - 2 - 1 DPS 0
- DPS
Reserved for future expansion Data Pointer Register Select DPS 0 1 Selects DPTR Registers DP0L, DP0H Selects DPTR Registers DP1L, DP1H
Memory Organization
Program Memory
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.
Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
Watchdog Timer (One-time Enabled with Reset-out) Using the WDT
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WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further information on the UART operation, refer to the Atmel Web site (http://www.atmel.com). From the home page, select "Products", then "Microcontrollers", then "8051-Architecture", then "Documentation", and "Other Documents". Open the Adobe(R) Acrobat(R) file "AT89 Series Hardware Description". Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers' operation, refer to the Atmel Web site (http://www.atmel.com). From the home page, select "Products", then "Microcontrollers", then "8051-Architecture", then "Documentation", and "Other Documents". Open the Adobe Acrobat file "AT89 Series Hardware Description". The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 4 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.
Timer 0 and 1
Interrupts
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.
Table 4. Interrupt Enable (IE) Register
(MSB) EA - - ES ET1 (LSB) EX1 ET0 EX0
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.
Symbol EA
Position IE.7
Function Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Reserved Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0 enable bit
- - ES ET1 EX1 ET0 EX0
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
User software should never write 1s to reserved bits, because they may be used in future AT89 products.
Figure 1. Interrupt Sources
0 INT0 1 IE0
TF0
0 INT1 1 IE1
TF1 TI RI
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Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 2. Oscillator Connections
C2 XTAL2
C1 XTAL1
GND
Note:
C1, C2 = =
30 pF 10 pF for Crystals 40 pF 10 pF for Ceramic Resonators
Figure 3. External Clock Drive Configuration
NC XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
GND
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Powerdown is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. 11
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Table 5. Status of External Pins During Idle and Power-down Modes
Mode Idle Idle Power-down Power-down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
Program Memory Lock Bits
The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Table 6. Lock Bit Protection Modes
Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U Protection Type No program lock features MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled Same as mode 2, but verify is also disabled Same as mode 3, but external execution is also disabled
3 4
P P
P P
U P
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.
Programming the Flash - Parallel Mode
The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89S51 code memory array is programmed byte-by-byte. Programming Algorithm: Before programming the AT89S51, the address, data, and control signals should be set up according to the Flash Programming Modes table (Table 7) and Figures 4 and 5. To program the AT89S51, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
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Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 51H indicates AT89S51 (200H) = 06H Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.
Programming the Flash - Serial Mode
The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz.
Serial Programming Algorithm
To program and verify the AT89S51 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to "H". If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16. 3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write cycle is self-timed and typically takes less than 0.5 ms at 5V. 4. Any memory location can be verified by using the Read instruction that returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal device operation. 13
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Power-off sequence (if needed): Set XTAL1 to "L" (if a crystal is not used). Set RST to "L". Turn VCC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO.
Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 8.
Programming Interface - Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. Most major worldwide programming vendors offer worldwide support for the Atmel AT89 microcontroller series. Please contact your local programming vendor for the appropriate software revision.
Table 7. Flash Programming Modes
ALE/ Mode Write Code Data Read Code Data Write Lock Bit 1 Write Lock Bit 2 Write Lock Bit 3 Read Lock Bits 1, 2, 3 Chip Erase Read Atmel ID Read Device ID Read Device ID VCC 5V 5V 5V 5V 5V RST H H H H H PSEN L L L
(3)
EA/ VPP 12V P2.6 L L H H H P2.7 H L H H L P3.3 H L H H H P3.6 H H H L H P3.7 H H H L L
P0.7-0 Data DIN DOUT X X X P0.2, P0.3, P0.4 X 1EH 51H 06H
P2.3-0
P1.7-0
PROG
(2)
Address A11-8 A11-8 X X X A7-0 A7-0 X X X
H
(3)
H 12V 12V
(3)
L L
12V
5V
H
L
H
(1)
H
H
H
L
H
L
X
X
5V 5V 5V 5V
H H H H
L L L L H H H
12V H H H
H L L L
L L L L
H L L L
L L L L
L L L L
X 0000 0001 0010
X 00H 00H 00H
Notes:
1. 2. 3. 4. 5.
Each PROG pulse is 200 ns - 500 ns for Chip Erase. Each PROG pulse is 200 ns - 500 ns for Write Code Data. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. RDY/BSY signal is output on P3.0 during programming. X = don't care.
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AT89S51
2487B-MICRO-12/03
AT89S51
Figure 4. Programming the Flash Memory (Parallel Mode)
VCC
AT89S51
ADDR. 0000H/FFFH A0 - A7 A8 - A11 P1.0-P1.7 P2.0 - P2.3 P2.6 P2.7 P3.3 P3.6 P3.7 XTAL2 EA VIH/VPP VCC P0 PGM DATA
SEE FLASH PROGRAMMING MODES TABLE
ALE
PROG
3-33 MHz P3.0
RDY/ BSY
XTAL1 GND
RST PSEN
VIH
Figure 5. Verifying the Flash Memory (Parallel Mode)
VCC
AT89S51
ADDR. 0000H/FFFH A0 - A7 A8 - A11 P1.0-P1.7 P2.0 - P2.3 P2.6 P2.7 P3.3 P3.6 P3.7 XTAL 2 VCC P0 PGM DATA (USE 10K PULLUPS)
SEE FLASH PROGRAMMING MODES TABLE
ALE VIH EA
3-33 MHz
XTAL1 GND
RST PSEN
VIH
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2487B-MICRO-12/03
Flash Programming and Verification Characteristics (Parallel Mode)
TA = 20C to 30C, VCC = 4.5 to 5.5V
Symbol Parameter Min Max Units
VPP IPP ICC 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQV tEHQZ tGHBL tWC
Programming Supply Voltage Programming Supply Current VCC Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold After PROG Data Setup to PROG Low Data Hold After PROG P2.7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold After PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE PROG High to BUSY Low Byte Write Cycle Time
11.5
12.5 10 30
V mA mA MHz
3 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 0.2
33
s s 1 48tCLCL 48tCLCL s
0
48tCLCL 1.0 50 s s
Figure 6. Flash Programming and Verification Waveforms - Parallel Mode
P1.0 - P1.7 P2.0 - P2.3 PORT 0
PROGRAMMING ADDRESS VERIFICATION ADDRESS
tAVQV
DATA IN DATA OUT
tAVGL
ALE/PROG
tDVGL
tGHDX
tGHAX tGHSL
LOGIC 1 LOGIC 0
tSHGL
VPP
tGLGH
EA/VPP
tEHSH
P2.7 (ENABLE)
tELQV tGHBL
tEHQZ
P3.0 (RDY/BSY)
BUSY
READY
tWC
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AT89S51
2487B-MICRO-12/03
AT89S51
Figure 7. Flash Memory Serial Downloading
VCC
AT89S51
VCC
INSTRUCTION INPUT DATA OUTPUT CLOCK IN
P1.5/MOSI P1.6/MISO P1.7/SCK
XTAL2
3-33 MHz
XTAL1 GND
RST
VIH
Flash Programming and Verification Waveforms - Serial Mode
Figure 8. Serial Programming Waveforms
7
6
5
4
3
2
1
0
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2487B-MICRO-12/03
Table 8. Serial Programming Instruction Set
Instruction Format Instruction Programming Enable Byte 1 1010 1100 Byte 2 0101 0011 Byte 3 xxxx xxxx Byte 4 xxxx xxxx 0110 1001 (Output on MISO) xxxx xxxx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Operation Enable Serial Programming while RST is high
Chip Erase Read Program Memory (Byte Mode) Write Program Memory (Byte Mode) Write Lock Bits(1) Read Lock Bits
1010 1100 0010 0000 0100 0000 1010 1100 0010 0100
100x xxxx
A11 A10 A9 A8
xxxx xxxx
A7 A6 A5 A4 A3 A2 A1 A0
Chip Erase Flash memory array Read data from Program memory in the byte mode Write data to Program memory in the byte mode Write Lock bits. See Note (1). xx Read back current status of the lock bits (a programmed lock bit reads back as a "1") Read Signature Byte Read data from Program memory in the Page Mode (256 bytes) Write data to Program memory in the Page Mode (256 bytes)
xxxx xxxx
1110 00
B1 B2
A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
xxxx xxxx xxxx xxxx
xxxx xxxx
LB3
xxxx xxxx
xxx
A11 A10 A9 A8
Read Program Memory (Page Mode) Write Program Memory (Page Mode) Note:
1. B1 = 0, B2 = 0 Mode 1, no lock protection Mode 2, lock bit 1 activated B1 = 0, B2 = 1 B1 = 1, B2 = 0 Mode 3, lock bit 2 activated Mode 4, lock bit 3 activated B1 = 1, B2 = 1
A11 A10 A9 A8
0101 0000
xxxx
A11 A10 A9 A8
0011 0000
xxxx
A7
Read Signature Bytes
0010 1000
xxxx
xxx xxx0
Signature Byte Byte 1... Byte 255 Byte 1... Byte 255
Byte 0
Byte 0
}
Each of the lock bit modes need to be activated sequentially before Mode 4 can be executed.
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1. For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded.
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AT89S51
2487B-MICRO-12/03
LB2 LB1
AT89S51
Serial Programming Characteristics
Figure 9. Serial Programming Timing
MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH
Table 9. Serial Programming Characteristics, TA = -40 C to 85 C, VCC = 4.0 - 5.5V (Unless Otherwise Noted)
Symbol 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV tERASE tSWC Parameter Oscillator Frequency Oscillator Period SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Chip Erase Instruction Cycle Time Serial Byte Write Cycle Time Min 3 30 8 tCLCL 8 tCLCL tCLCL 2 tCLCL 10 16 32 500 64 tCLCL + 400 Typ Max 33 Units MHz ns ns ns ns ns ns ms s
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2487B-MICRO-12/03
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 15.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
The values shown in this table are valid for TA = -40C to 85C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol VIL VIL1 VIH VIH1 VOL VOL1 VOH Parameter Input Low Voltage Input Low Voltage (EA) Input High Voltage Input High Voltage Output Low Voltage(1) (Ports 1,2,3) Output Low Voltage(1) (Port 0, ALE, PSEN) Output High Voltage (Ports 1,2,3, ALE, PSEN) (Except XTAL1, RST) (XTAL1, RST) IOL = 1.6 mA IOL = 3.2 mA IOH = -60 A, VCC = 5V 10% IOH = -25 A IOH = -10 A IOH = -800 A, VCC = 5V 10% VOH1 IIL ITL ILI RRST CIO ICC Notes: Output High Voltage (Port 0 in External Bus Mode) Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current Power-down Mode
(2)
Condition (Except EA)
Min -0.5 -0.5 0.2 VCC+0.9 0.7 VCC
Max 0.2 VCC-0.1 0.2 VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45
Units V V V V V V V V V V V V
2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650
IOH = -300 A IOH = -80 A VIN = 0.45V VIN = 2V, VCC = 5V 10% 0.45 < VIN < VCC
A A A K pF mA mA A
10 50 300 10 25 6.5 50
Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz Idle Mode, 12 MHz VCC = 5.5V
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V.
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AT89S51
2487B-MICRO-12/03
AT89S51
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Valid to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE High 43 200 203 23 433 33 0 123 tCLCL-25 0 97 517 585 300 3tCLCL-50 4tCLCL-75 tCLCL-30 7tCLCL-130 tCLCL-25 0 tCLCL+25 400 400 252 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 75 312 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 59 tCLCL-8 5tCLCL-80 10 43 205 145 0 tCLCL-25 127 43 48 233 tCLCL-25 3tCLCL-45 3tCLCL-60 Min Max Variable Oscillator Min 0 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 Max 33 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
21
2487B-MICRO-12/03
External Program Memory Read Cycle
tLHLL ALE tAVLL PSEN tPLAZ tLLAX PORT 0
A0 - A7
tLLPL
tLLIV tPLIV
tPLPH
tPXAV tPXIZ tPXIX
INSTR IN A0 - A7
tAVIV PORT 2
A8 - A15 A8 - A15
External Data Memory Read Cycle
tLHLL ALE tWHLH PSEN tLLDV tLLWL RD tAVLL PORT 0 tLLAX tRLAZ
DATA IN
tRLRH
tRLDV
tRHDZ tRHDX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL tAVDV PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
22
AT89S51
2487B-MICRO-12/03
AT89S51
External Data Memory Write Cycle
tLHLL ALE tWHLH PSEN tLLWL WR tAVLL PORT 0 tLLAX tQVWX tWLWH
tQVWH
DATA OUT
tWHQX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
VCC - 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V
tCHCX tCLCH tCHCL
tCLCX tCLCL
External Clock Drive
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 30 12 12 5 5 Max 33 Units MHz ns ns ns ns ns
23
2487B-MICRO-12/03
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 1.0 700 50 0 700 Max Variable Oscillator Min 12tCLCL 10tCLCL-133 2tCLCL-80 0 10tCLCL-133 Max Units s ns ns ns ns
Shift Register Mode Timing Waveforms
INSTRUCTION ALE CLOCK 0 1 2 3 4 5 6 7 8
tXLXL tQVXH
WRITE TO SBUF
tXHQX
0 1 2 3 4 5 6 7 SET TI
VALID VALID VALID VALID VALID
OUTPUT DATA CLEAR RI INPUT DATA
tXHDV
VALID VALID
tXHDX
VALID
SET RI
AC Testing Input/Output Waveforms(1)
VCC - 0.5V 0.2 VCC + 0.9V TEST POINTS 0.45V 0.2 VCC - 0.1V
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
V LOAD+ V LOAD V LOAD 0.1V 0.1V
V OL Timing Reference Points V OL +
0.1V
0.1V
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
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AT89S51
2487B-MICRO-12/03
AT89S51
Ordering Information
Speed (MHz) 24 Power Supply 4.0V to 5.5V Ordering Code AT89S51-24AC AT89S51-24JC AT89S51-24PC AT89S51-24SC AT89S51-24AI AT89S51-24JI AT89S51-24PI AT89S51-24SI 33 4.5V to 5.5V AT89S51-33AC AT89S51-33JC AT89S51-33PC AT89S51-33SC Package 44A 44J 40P6 42PS6 44A 44J 40P6 42PS6 44A 44J 40P6 42PS6 Operation Range Commercial (0 C to 70 C)
Industrial (-40 C to 85 C)
Commercial (0 C to 70 C)
Package Type 44A 44J 40P6 42PS6 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 42-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
25
2487B-MICRO-12/03
Packaging Information
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
26
AT89S51
2487B-MICRO-12/03
AT89S51
44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
27
2487B-MICRO-12/03
40P6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B
R
28
AT89S51
2487B-MICRO-12/03
AT89S51
42PS6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.51 36.70 15.24 13.46 0.38 0.76 3.05 0.20 - NOM - - - - - - - - - - 1.78 TYP MAX 4.83 - 36.96 15.88 13.97 0.56 1.27 3.43 0.30 18.55 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
11/6/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 42PS6, 42-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 42PS6 REV. A
R
29
2487B-MICRO-12/03
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2487B-MICRO-12/03

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